1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and an apparatus for driving on-chip wires through capacitive coupling.
2. Related Art
Sending a high bandwidth data signal across a VLSI chip typically requires a large amount of energy. In fact, in certain scenarios, it can overwhelm mechanisms for both power delivery and heat removal. For example, on a 130 nm chip, running at 1.3V and 3 GHz, transmitting a single bit of data across a 1 cm chip edge consumes over 3 mW of power (assuming typically spaced repeaters along the wire length). Aggregating 10,000 of these wires together in a series of wide buses can consume 30 W to simply switch signals across the wires. It is obviously impractical to consume such large amounts of energy for simply communicating across a chip.
Reducing the voltage swing on these long wires can reduce the energy required to switch signals across the long wires. This is because the energy required to switch a wire is proportional to the voltage swing ΔV. Hence, reducing the voltage swing by 10× reduces the energy by 10× as well. (Note that if the power supply voltage V is also reduced by 10×, the energy will be reduced by 100×:10× due to the reduced voltage swing and 10× due to the reduced power supply voltage.)
Note that, to operate properly, other components on the chip must still run at the full power supply voltage. Hence, the above approach to reduce the power consumption requires a way to reduce the voltage swing on just the wires, and not across the whole chip.
Currently, there are three popular schemes to reduce the voltage swing for on-chip wires.
In the first scheme, the chip uses a secondary power supply to drive long on-chip wires. For example, all transistors driving the long wires can use a secondary power supply at 130 mV, while the rest of the chip uses the primary supply at 1.3V. This scheme provides a significant reduction of energy consumption on the wire, because energy is proportional to the product of ΔV and Vsupply. In the above example, the energy consumption is reduced by a factor of 100×: a factor of 10× due to the reduced voltage swing and another factor of 10× due to the reduced power supply.
The problem with this scheme is that it is difficult to design a power grid with the requisite power supply impedance. The power supply impedance is constrained by the allowable voltage “sag” during a peak transient current. Hence, if the voltage of a power supply grid is lowered, the impedance of the power supply must also be correspondingly lowered. Today's high-performance chips have power supply impedances in the milliohms, and designing power grids at these low impedances is already quite expensive. Further reducing the impedance to tenths of milliohms is prohibitively difficult and expensive.
The second scheme to limit voltage swings uses circuits that cut themselves off when driving wires. These circuits use transistors to drive the wire voltage, and when the wire voltage exceeds a cutoff threshold, the transistors turn themselves off. Alternatively, the circuits can use a timing signal to turn themselves off, where this timing signal is designed to match a desired signal swing. The problem with both of these types of circuits is that their swings are not well-controlled and are subject to process, voltage, and temperature variations. To ensure that they work under extreme conditions, these circuits require margining, which greatly reduces their potential energy savings.
For example, a problem can arise if cutoff circuits sense driver-end voltages, which are poorly-matched to voltages at the receiver end of a long wire. This can cause cut-off circuits to switch improperly. Also, timing signals suffer from skew and jitter across wide data-paths. Both of these problems require significant over-design to ensure signal integrity, thereby sacrificing potential energy savings.
In the third scheme, designers can “stack” gates atop each other so that they share the power supply serially. For example, two gates can be stacked atop each other, so that the bottom gate is powered between Ground and Vsupply2, and the top gate is powered between Vsupply2 and Vsupply. This idea can be extended to multiple gates.
However, this scheme complicates the receiver design because different receivers must have different common-mode voltage levels. In the simple example above, receivers for the two gates must be biased to receive data at either the low range or the high range, which leads to multiple receiver designs and wide delay variances between bits.
Hence, what is needed is a method that reduces the power consumed while transferring signals across long on-chip wires without the disadvantages of the schemes described above.